TSMC 3nm (N3E) 1.2V/1.8V I3C Libraries, multiple metalstacks
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PCIe 7.0 Controller
The Rambus PCI Express® (PCIe®) 7.0 Controller is a configurable and scalable design for ASIC implementations. It is backward compatible to the PCIe 6.0 and 5.0, as well as version 6.2.1 PHY Interface for PCI Express (PIPE) specification.
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PCIe 7.0 IP
- PCIe 7.0 PHY IP supporting the latest features of the evolving PCIe 7.0 specification to enable 128 GT/s and up to x16 lane configurations
- PCIe 7.0 PHY in TSMC (N5, N3P, N2P)
- PCIe 7.0 Controller with AXI
- PCIe 7.0 Retimer Controller
- PCIe 7.0 Switch
- PCIe 7.0 Controller (can be configured to support EP, RP, DM, or SW applications)