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PCIe 6.0 PHY (5nm)
The PCIe PHY IP consists of hardmacro PMA and softmacro PMD compliant to PCIe Base 6.0 specification. This IP offers a cost-effective and low-power solution using 5nm FinFet CMOS technology. It includes all ESD I/Os and bump pads, and supports extensive built-in self test features such as loopback and scan.
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Block Diagram of the PCIe 6.0 PHY (5nm)
PCIe 6.0 IP
- PCIe 6.0 Integrity and Data Encryption Security Module
- PCIe 6.0 PHY in TSMC (N6, N5, N4P, N3P, N3E)
- PCIe 6.0 PHY in Samsung (SF5A, SF4X, SF2)
- PCIe 6.1 Controller
- 1 to 64 Gbps PCI-Express (PCIe) 6.0 and CXL 3.0 PHY
- Configurable controllers for PCIe 6.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications