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PCIe 6.0 Controller EP/RP/DM/SW with AMBA bridge & HPC features, including Arm Confidential Compute Architecture
The configurable and scalable Synopsys Controller IP for PCI Express® (PCIe®)
6.0 supports all required features of the PCI Express 6.0 specifications, and can be configured by the user to support Endpoint (EP), Root Port, Dual Mode (DM), or Switch Port (SW) applications. The low-latency controller with new MultiStream architecture allows a full 64GT/s x16 lane bandwidth with support for up to 1024-bit data paths, while enabling timing closure at 1GHz. The controller can ensure optimal flow with multiple sources and in
multivirtual channel implementations. Support for host, device, and dual mode enables early interoperability in absence of available 6.0 hosts and interop partners. Designers can achieve maximum throughput for Arm-based SoCs with the controller’s support for the Arm AXI and for advanced host features including deferrable memory writes. The controller's reliability, availability
and serviceability (RAS) features enhance data integrity, simplify firmware development and improve link bring-up.
The Synopsys Controller IP for PCIe 6.0 seamlessly interoperates with the silicon-proven PHY IP for PCIe 6.0 in advanced FinFET processes to provide a low-risk solution that designers can use to accelerate time-to-market and efficiently deliver differentiated products that require the 64GT/s PCIe 6.0 technology. To protect against data tampering and physical attacks in high- performance computing SoCs using the PCIe 6.0 interface, Synopsys offers standards-compliant IDE Security IP Modules.
6.0 supports all required features of the PCI Express 6.0 specifications, and can be configured by the user to support Endpoint (EP), Root Port, Dual Mode (DM), or Switch Port (SW) applications. The low-latency controller with new MultiStream architecture allows a full 64GT/s x16 lane bandwidth with support for up to 1024-bit data paths, while enabling timing closure at 1GHz. The controller can ensure optimal flow with multiple sources and in
multivirtual channel implementations. Support for host, device, and dual mode enables early interoperability in absence of available 6.0 hosts and interop partners. Designers can achieve maximum throughput for Arm-based SoCs with the controller’s support for the Arm AXI and for advanced host features including deferrable memory writes. The controller's reliability, availability
and serviceability (RAS) features enhance data integrity, simplify firmware development and improve link bring-up.
The Synopsys Controller IP for PCIe 6.0 seamlessly interoperates with the silicon-proven PHY IP for PCIe 6.0 in advanced FinFET processes to provide a low-risk solution that designers can use to accelerate time-to-market and efficiently deliver differentiated products that require the 64GT/s PCIe 6.0 technology. To protect against data tampering and physical attacks in high- performance computing SoCs using the PCIe 6.0 interface, Synopsys offers standards-compliant IDE Security IP Modules.
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