The multi-channel DesignWare® PHY IP for PCI Express® (PCIe®) 5.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s demands for higher bandwidth. The PHY meets the needs of today’s high-speed chipto-chip, board-to-board, and backplane interfaces while being extremely low in power and area.
Using leading-edge design, analysis, simulation, and measurement techniques, Synopsys delivers exceptional signal integrity and jitter performance that exceeds the PCI Express standard’s electrical specifications. The high-margin, robust PHY architecture tolerates process, voltage and temperature (PVT) manufacturing variations and is implemented with standard CMOS digital process technologies.
The multi-tap transmitter and receiver equalizers, along with the advanced built-in diagnostics and ATE test vectors, enable customers to control, monitor and test for signal integrity without the need for expensive test equipment. This provides on-chip visibility into actual link and channel performance to quickly improve signal integrity, reducing both product development cycles and the need for costly field support.
Physical Coding Sublayer (PCS) block with PIPE interface
PCIe power management features, including L1 substate; power gating and power island; DFE bypass option and voltage mode Tx with under drive supply options
The multi-channel PHY macro with single clock and control core for higher density with support for both internal and external reference clock inputs
PIPE bifurcation as well as PHY macro aggregation for up to 16-lane configurations
Superior Rx jitter & cross talk tolerance reduces design constraints for a wider range of board layout designs
Automated Test Equipment (ATE) test vectors for complete at-speed production testing
Each PHY channel contains its own 7-, 9-, 11-, 15-, 16-, 23-, and 31-bit pseudo random bit sequencer (PRBS) for internal and external loopbacks Each channel is fully controllable via the integrated logic core as well as the test access port (TAP)
Supports all required features of the PCIe® 5.0, 4.0, 3.1, 2.1, 1.1, and PIPE specifications
x1, x2, x4, x8, x16 lane configurations with bifurcation
Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE) supporting more than 36dB channel loss
Adaptive receiver equalizer with programmable settings
Supports lane margining at the receiver
Supports L1 substate power management
Embedded Bit Error Rate (BER) tester and internal eye monitor
Built-in Self Test vectors, PRBS generation and checker
IEEE 1149.6 AC JTAG Boundary Scan
Supports -40°C to 125°C junction temperatures
Supports flip-chip packaging
Liberty timing views (.lib)
LEF abstracts (.lef)
CDL netlist (.cdl)
ATPG models IBIS-AMI models
Desktops, workstations, servers
Embedded systems and set-top boxes
Network switches and routers
Enterprise computing and storage networks
Video Demo of the PCIe 5.0 PHY in TSMC (16nm)
This video features Synopsys’ DesignWare PHY IP for PCI Express 5.0 meeting the Rev. 1.0 specification’s channel performance and jitter tolerance. The IP operates at 32GT/s data rate and exceeds the required 36 dB channel loss to enable high-throughput over the toughest, long-reach channels. Accelerate your move to PCI Express 5.0 with Synopsys’ DesignWare IP.