Block Diagram of the PCIe 5.0,4.0,3.1 / 3.0根端口，端点，双模，具有Native用 户界面的交换机端口Controller IP核
Video Demo of the PCIe 5.0,4.0,3.1 / 3.0根端口，端点，双模，具有Native用 户界面的交换机端口Controller IP核
The demo showcases stable PCIe 5.0 Link Training (32 GT/s) and exceptional signal integrity with a Broadcom® PCIe 5.0 PHY platform.
This solution is based on the XpressRICH® IP Controller for PCIe 5.0 combined with Broadcom’s PCIe 5.0 PHY IP. Several different setups demonstrate that the combined IPs provide exceptional signal integrity with, robust link training at 32 GT/s and stable backward compatibility at PCIe 4.0, PCIe 3.0, PCIe 2.0 and PCIe 1.0 speeds. The results of these tests is a quality guarantee for the SoC designers who choose the combined solution of PLDA’s PCIe 5.0 Controller and Broadcom’s PHY IP.