UCIe-S PHY for Standard Package (x16) in Samsung (SF5A, SF4X, SF2)
PCIe 3.1/2.1 PHY (6nm, 7nm, 12nm, 14nm, 16nm, 22nm, 28nm, 40nm and 55nm)
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PCI Express PHY IP
- PCIe 7.0 PHY IP supporting the latest features of the evolving PCIe 7.0 specification to enable 128 GT/s and up to x16 lane configurations
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- PCIe 4.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
- PCIe 4.0 Controller with AMBA AXI interface
- PCI Express PHY serial link PIPE Transceiver IP cell/hard macro
- PCI Express GEN-3/Display Port SERDES PHY - Samsung 28 28LPP