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PCIe 2.1 PHY in TSMC(12nm,16nm, 28nm, 40nm)
M31 PCIe 2.1 transceiver IP provides a complete range of PCIe 2.1 Base
applications. It is compliant with the PIPE 3.0 specification. This IP integrates high-speed mixed signal circuits to support PCIe 2.1 traffic at 5Gbps and is backward compatible with PCIe 1.1 data rate at 2.5Gbps. It is optimized for minimal die area and low power consumption. With the supports for both TX and RX equalization techniques, the PCIe 2.1 IP can meet the requirements for different channel conditions.
applications. It is compliant with the PIPE 3.0 specification. This IP integrates high-speed mixed signal circuits to support PCIe 2.1 traffic at 5Gbps and is backward compatible with PCIe 1.1 data rate at 2.5Gbps. It is optimized for minimal die area and low power consumption. With the supports for both TX and RX equalization techniques, the PCIe 2.1 IP can meet the requirements for different channel conditions.
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PCI Express PHY IP
- PHY/PCS Logical Sub-Block IP Core for PCIe supporting PCIe 5.0, 4.0, 3.1 PHY/PMA and compliant to the PIPE 5.2 and 4.4.1 Specifications
- PCIe 2.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
- PCIe 3.0, 2.1, 1.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
- PCIe 5.0 PHY in TSMC (16nm)
- PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- PCIe4 Ethernet SERDES PHY - TSMC N5