PCIe 2.0 Serdes PHY IP,在 SMIC 28HKMG 中经过硅验证
PCIe2.0 PHY IP收发器为低功耗和较小的模具面积进行了优化,同时保持了良好的性能和数据吞吐量。PCIe2.0 PHY IP的交付件包含带有ESD保护的片上物理收发器解决方案,内置的自测试模块(具有内置的抖动注入功能)以及动态均衡电路,能够全面支持高性能配置的需求
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Block Diagram of the PCIe 2.0 Serdes PHY IP,在 SMIC 28HKMG 中经过硅验证
PCIe 2.0 IP
- PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- Compute Express Link (CXL) 1.1/2.0/3.0 Controller
- PCIe 2.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
- CXL 2.0 Agilex FPGA Acclerator Card
- PCIe 2.0 PHY in Fujitsu (40nm)
- PCIe 2.0 PHY in SMIC (40nm, 28nm)