Scalable multicore architecture for a range of macrocells, small cells, cloud-RAN, DFE/DPD/ and more
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PCIe 2.0 End Point IP Core - PCIe with FIFO Interface
The Arasan PCI Express End Point is a high-speed, high-performance, and lowpowerIP core that is fully compliant to the PCI Express Specification 1.1 and 2.0. The IP core is designed for applications in computing, networking, storage, servers, wireless, and consumer electronics. The feature-rich IP core is highly configurable that allows a target design to be implemented with the least number of gates and highest performance.
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Block Diagram of the PCIe 2.0 End Point IP Core - PCIe with FIFO Interface
PCI PCI Express IP
- PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- PCIe 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- Gen5 PCIe Hybrid Controller with SR-IOV and ARI Support
- Gen5 PCIe Transparent Switch
- PCIe 4.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
- PHY/PCS Logical Sub-Block IP Core for PCIe supporting PCIe 5.0, 4.0, 3.1 PHY/PMA and compliant to the PIPE 5.2 and 4.4.1 Specifications