MIPI C-PHY v1.2 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (16nm,N6, N5)
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PCI Express (PCIe) 6.0 Controller
Application-optimized, high-performance controller IP for PCIe
The Cadence® Controller IP for PCIe 6.0 provides the logic required to integrate a root complex (RC), endpoint (EP), or dual mode (DM) controller into any system-on-chip (SoC). Compliant with PCIe 6.0, 5.0, 4.0, 3.1, 2.1, and 1.1 specifications.
The Cadence® Controller IP for PCIe 6.0 provides the logic required to integrate a root complex (RC), endpoint (EP), or dual mode (DM) controller into any system-on-chip (SoC). Compliant with PCIe 6.0, 5.0, 4.0, 3.1, 2.1, and 1.1 specifications.
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