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PCI Express GEN-3/Display Port SERDES PHY - Samsung 28 28LPP
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protocol market needs including a wide range of ac- coupled high-speed serial communication standards requiring serial Clock Data Recovery (CDR). The pin-configurable macro uses standard logic process devices, and exhibits exceptional input sensitivity, input jitter tolerance and low output jitter. Analog Bits proprietary and industry leading PLL technology in combination with sophisticated circuit techniques and innovative IO design makes this macro an extremely area and power efficient solution. The PMA can be integrated with the available PCS to provide a PCI-Express Gen1/Gen2 PHY solution, and has interface capability to allow integration with other customer-designed serial protocol PCS layers.
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SERDES IP
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- Low-Latency SerDes PMA - 10GbE, 25GbE
- Multi-protocol SerDes PMA - PCIe1 PCIe2 PCIe3 PCIe4 PCIe5 and more
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- 400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency