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PCI Express Differential Buffer IP, Single - Ended, UMC 90nm SP process
100MHz Reference Clock Single-end to Differential Buffer for PCIE Gen.II, UMC 55nm SP/RVT Low-K Logic process.
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PCIe PHY IP
- PCIe 6.0 PHY in TSMC (N6, N5, N3P, N3E)
- PCIe 6.0 PHY in Samsung (SF5A, SF4X, SF2)
- PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- PHY/PCS Logical Sub-Block IP Core for PCIe supporting PCIe 5.0, 4.0, 3.1 PHY/PMA and compliant to the PIPE 5.2 and 4.4.1 Specifications
- PCIe 4.0 PHY in TSMC (28nm, 16nm, 12nm, N7, N3P)
- PCIe 5.0 PHY in TSMC (16nm, 12nm, N7, N6, N5, N3E, N3P)