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PCI Express - Configurable PCI Express 4.0 IP
The Renesas PCIe 4.0 Dual Mode Link Controller IP is compliant with the "PCI Express (PCIe) 4.0 Base Specification". This IP supports the major functions required as PCIe link IP for embedded systems. The system interface of this IP is based on the "AMBA® AXI Protocol specification v1.0" ARM IHI 0022B and the "PHY Interface For the PCI Express, SATA, and USB3.1 Architectures (PIPE) 4.4.1 Specification". This IP has many configurable parameters for each product.
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Block Diagram of the PCI Express - Configurable PCI Express 4.0 IP
PCI IP
- PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- PCIe 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- Gen5 PCIe Hybrid Controller with SR-IOV and ARI Support
- Gen5 PCIe Transparent Switch
- PCIe 4.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
- PHY/PCS Logical Sub-Block IP Core for PCIe supporting PCIe 5.0, 4.0, 3.1 PHY/PMA and compliant to the PIPE 5.2 and 4.4.1 Specifications