PCI Compiler, 32-bit Master/Target
Altera?s PCI MegaCore functions are fully tested to meet the requirements of the PCI-SIG PCI Local Bus Specification, Revision 3.0 and Compliance Checklist, Revision 3.0. You can test drive Altera PCI MegaCore functions using the OpenCore Plus feature to compile, simulate, and hardware-test the functions within your custom logic. When you are ready to license a function, contact your local Altera sales representative.
The pci_mt32 and pci_t32 MegaCore functions provide fully compliant, 32 bit, 66 MHz PCI bus interface support. The pci_mt32 and pci_t32 cores are optimized for the Stratix® FPGA series, Arria® GX FPGA series, Cyclone® FPGA series, and the HardCopy® ASICs series. Additionally, the pci_mt32 and pci_t32 cores are optimized for MAX® II CPLDs.
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PCI IP
- PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- PCIe 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- PCIe 4.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
- PHY/PCS Logical Sub-Block IP Core for PCIe supporting PCIe 5.0, 4.0, 3.1 PHY/PMA and compliant to the PIPE 5.2 and 4.4.1 Specifications
- PCIe 2.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
- PCIe 3.0, 2.1, 1.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support