Parallel FFT

特色

• Fastest most power efficient architecture optimized for short FFTs, 4 to 64 points
• Optimized Butterflies/Dragonflies, reductions from constant twiddle factors reduces logic
• No pipeline limit, fully asynchronous to maximum pipeline stages
• N points in/out per clock cycle, ultra high performance, 25 GSPS+ possible in FPGA
• lengths up to 64 points practical in FPGAs