创飞芯OTP IPs可适用于不同的技术代(0.13/0.11 / 0.16 / 0.18微米和90/65/55/40/28纳米),可以很容易地移植到衍生逻辑技术，如射频、模拟、高压CMOS图像传感器和嵌入式闪存或EEPROM等，不需要改变工艺步骤或设备

Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The required voltage for OTP bit cell programming can be supplied from internal charge pump or external VPP pin. The bit cell is programmed by applying a high-voltage pulse across the gate and substrate of the thin oxide transistor to break down the oxide between gate and substrate. Before programming, a blank OTP array comes with all bits reading as "0". After programming, an OTP bit cell will to be read as "1".

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