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OTP
Rangduru’s DX OTP Macro is a field programmable Non-Volatile Memory(NVM) macro using 0.5T bit cell technology, which is smaller than the conventional technology like 1T/2T bit cell.
The half transistor(0.5T) bit cell technology provides better bit cost, higher reliability and lower overall product cost than NOR flash.
The DX OTPTM provides this reduced cost and increased density through innovative ability to use standard semiconductor logic processes, with just one extra mask. This avoids the costly use of non-standard processes.
Additionally, the DX OTPTM enables large capacity onchip NVM solution for MCUs/SoCs, hence opening new high density on-chip NVM applications requiring high speed, low power consumption, high secuirty, space reduction, and low cost in total system.
The half transistor(0.5T) bit cell technology provides better bit cost, higher reliability and lower overall product cost than NOR flash.
The DX OTPTM provides this reduced cost and increased density through innovative ability to use standard semiconductor logic processes, with just one extra mask. This avoids the costly use of non-standard processes.
Additionally, the DX OTPTM enables large capacity onchip NVM solution for MCUs/SoCs, hence opening new high density on-chip NVM applications requiring high speed, low power consumption, high secuirty, space reduction, and low cost in total system.
查看 OTP 详细介绍：
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Block Diagram of the OTP
OTP IP
- 512x8 Bits OTP (One-Time Programmable) IP, TSMC 12FFC 0.8V/1.8V Process
- NVM OTP in Fujitsu (90nm, 65nm, 55nm, 40nm)
- NVM OTP in Dongbu (180nm, 150nm, 110nm)
- NVM OTP in SMIC (110nm, 65nm, 55nm, 40nm)
- NVM OTP in TSMC (180nm, 152nm, 130nm, 110nm, 90nm, 65nm, 55nm, 40nm, 28nm, 22nm, 16nm, 12nm, N7, N6, N5, N4P)
- NVM OTP in UMC (180nm, 153nm, 110nm, 90nm, 80nm, 55nm, 40nm, 28nm, 22nm)