MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
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ONFI 4.1 PHY IP（硅经TSMC 12FFC验证）
ONFI PHY IP能够通过NAND闪存接口传输信号，或通过Flash控制器IP从NAND Flash接收数据。MDLL为PHY的控制信号设定延迟时间，以便在合适的时间段内访问闪存中的数据。请参考下图，了解ONFI PHY的架构
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Block Diagram of the ONFI 4.1 PHY IP（硅经TSMC 12FFC验证）
ONFI 4.1 PHY IP IP
- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 16nm
- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 12nm
- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 28nm
- ONFi PHY 4.0 (FPHY+MDLL+SDLL Regulator) (Silicon Proven in TSMC 28HPC+)
- Supporting ONFI 5.0, 4.2, 4.1, 4.0 and ONFI 3 - TSMC 5nm 5FF
- Supporting ONFI 5.0, 4.2, 4.1, 4.0 and ONFI 3 - TSMC 6nm 6FF