You are here:
One Port Register File Compiler IP, UMC 55nm SP process
UMC 55nm Standard Performance Low-K Logic process synchronous Single Port Register File SRAM using 0.425-Bit cell memory compiler.
查看 One Port Register File Compiler IP, UMC 55nm SP process 详细介绍:
- 查看 One Port Register File Compiler IP, UMC 55nm SP process 完整数据手册
- 联系 One Port Register File Compiler IP, UMC 55nm SP process 供应商