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One Port Register File Compiler IP, UMC 55nm SP process
UMC 55nm Standard Performance Low-K Logic process synchronous Single Port Register File SRAM using 0.425-Bit cell memory compiler.
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Memory IP
- The SST SuperFlash® IP is an embedded CMOS Flash memory IP with sector/chip Erase and byte Program capability.
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- High-Speed, High-Density and Low Power Memory Compilers and Logic Libraries for TSMC (65nm, 40nm, 28nm, 16nm)
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