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On-chip Nonvolatile APB Memory Controller

CoreApbNvm allows advanced microcontroller bus architecture (AMBA) Peripheral Bus (APB) access to the Microsemi Fusion nonvolatile memory (NVM), using a simple register-based access scheme. The core is designed to be configurable for use in various applications, using variable APB bus widths and a number of NVM instances (where supported). In addition, CoreApbNvm contains an Init/Config block which is used on reset to initialize RAM with the contents of NVM0. After reset, the Init/Config block can also be used to copy a user-specified number of words from NVM, starting at a user-specified base address.

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On-chip Nonvolatile APB Memory Controller IP

Simple Micro APB Bus Controller

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On-chip Nonvolatile APB Memory Controller

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On-chip Nonvolatile APB Memory Controller IP

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