On-chip APB SRAM Memory Controller

CoreAPBSRAM provides an APB bus interface to the embedded SRAM memory blocks within Microsemi's Flash devices. In these devices, software running on an APB-based microprocessor will be able to read and write the embedded SRAM. CoreAPBSRAM implements a standard Slave APB Bus 32-bit hardware interface. The core supports the ability to logically merge multiple SRAM blocks into one large area of SRAM.

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