The Cadence IP for Octal SPI Flash Controller and PHY supports the fastest frequency at 200MHz, with DDR Mode and DTR Protocol (including Octal DDR protocol with DQS for Octal SPI Devices) enabling data transfer rates up to 400Mbps with reduced read latency including support for Octal DDR protocol with DQS for Octal SPI devices.
The integrated soft PHY enables the highest speed clock rates, while eliminating the need for a reference clock at 4 times (4x) the bus clockin SDR mode and an 8x clock in DDR mode. That simplifies the SoC design, reduces the complexity of additional clock domains, and reduces the power consumption by the OSPI bus.
Flash memory is being utilized more frequently in computers and electronic devices found in Automotive, IoT, Connected Home, and other emerging applications, which demand ever higher transfer rates and lower latency. Expanding the flash Serial Peripheral Interface (SPI) accesses from the current 4 I/Os (Quad SPI) to 8 I/Os (Octal SPI) increased the Serial NOR Flash throughput and provide a more efficient solution for emerging applications, while providing backwards compatibility to QSPI devices with support for single, dual, quad, or octal I/O instructions.