2.5D Multi-Core Raster & Vector Graphics Processor for low-power SoCs with Microcontroller
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Multi State Viterbi Decoder IP Core
The Multi State Viterbi Decoder IP Core is a low complexity 16, 32, 64 or 256 state error control decoder using the maximum likelihood Viterbi algorithm. The decoder is designed for maximum flexibility, allowing it to decode various communications standards, as well as custom coding solutions.
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