Multi-Protocol Physical Medium Attachment Sublayer (PMA)

特色

• Full-duplex transceivers at serial data rates between 600 Mbps and 6.5 Gbps.
• Modular channels that has the configuration flexibility for any of the 3 mode below:
• data lane
• TX clock generator (using the RX PLL)
• ref clock input
• Additional LC PLL in common block to provide clocking flexibility
• Supports wide range of input reference clock from 25 MHz to 700 MHz
• Ability to dynamically reconfigure PMA blocks during run time
• Utilize GlobalFoundries 65nm LPe technology
• Requires supply voltage level of 1.2V and 2.5V on second PMA voltage supply
• Application support for multiple standards (see section 0)
• Selectable receiver and transmitter on-chip termination resistors of 42.5, 50, 60, 75 ohm (single-ended) termination with automatic calibration
• Receiver equalization (8 bits) up to 16dB
• Transmitter de-emphasis up to -12dB
• Receiver loss-of-signal indicator
• Support receiver detection for PCIe.
• Support PCIe electrical idle specifications.
• Beacon signaling for PCIe.
• PCIe rate switch circuitry
• IEEE 1149.1(DC) and 1149.6 (AC) JTAG boundary scan support

可交付内容

• Hard-IP - physical layout (GDSII) for GlobalFoundries 65nm LPE process
• LVS/CDL netlists
• Verilog simulation models (Tetramax and ATPG compatible)
• Synopsys Liberty files
• Physical LEF (Cadence)
• Specification, integration, and usage documentation
• Verilog RTL and SDC for PCS layer
• Encrypted SPICE model for signal integrity simulation*

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