MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
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Multi-Protocol Physical Coding Sublayer
特色
- Supported Protocol Standards
- PCI Express Gen1, Gen2, Gen 3
- PHY Interface for the PCI Express (PIPE) 2.0
- 1G Ethernet (GIGE)
- 10G Ethernet (XAUI)
- SATA 3.0 with OOB (Tx and Rx)
- SAS 4 with OOB (Tx and Rx)
- CPRI/JESD204B
- 10G Base-R
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12.5Gbps IP
- Bi-directional High speed interface lane up to 12.5Gbps
- Multi Protocol SERDES operating at up to 12.5Gbps (40nm TSMC)
- Multi Standard programmable SERDES PHY with single/multi-lane configurations with support of long-reach channel
- ARM HSSTP PHY with Link Layer
- Multi-Protocol Physical Medium Attachment Sublayer
- 0.6G - 12.5G Universal SerDes