MIPI D-PHY Rx-Only 2 Lanes in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, N7, N6)
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Multi-channel Limited Baseline HDTV 1080p H.264/AVC Decoder
The OL_H264MCLD core is a hardware implementation of the H.264 baseline video compression algorithm.
The core decodes a bitstream produced by the OLH264e encoder and produces a video stream up to the highest HDTV resolution.
Simple, fully synchronous design with low gate count.
The core decodes a bitstream produced by the OLH264e encoder and produces a video stream up to the highest HDTV resolution.
Simple, fully synchronous design with low gate count.
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