The Multi-2 Descrambler IP core implements the MULTI2 encryption/decryption algorithms as specified by ISO9979/0009 algorithm register entry (ISO standard 9979 MULTI2).
MULTI2 is a block cipher, developed by Hitachi in 1988. It is designed for general-purpose cryptography, but its current use is encryption/decryption of high-definition terrestrial/BS/CS broadcasts in Japan.
- Supports the MULTI2 block cipher algorithm as specified by ISO9979/0009
- Supports CBC and OFB cipher modes of operation as specified by NIST SP800-38A
- Supports variable number of rounds, programmable in multiples of 8 up to 256 rounds
- Designed especially for low power and low hardware resource area in ASIC.
- Scrambling/Descrambling data throughput is 173Mbps at clock 54MHz in case of 32 rounds.
- HERA support felexible SDK also, it can watch out to user that debugging real field TS information and RF side status.
- Verilog RTL Source code
- Verilog Simulation test-bench with example test vectors
- MULTI2 test C program and test vectors for H/W verification
- Example ModelSim simulation scripts & HERA MULTI2 Core User Guide