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MPEG TS Serializer
The MVD MPEG TS Serializer core is a drop-in module that includes the following functions:
• Incoming MPEG_TS clock resynchronization
• x47 sync signal recovery
• Parallel/Serial Conversion
• Auto adaptation to 188/204/208 bytes packet Input
• 188 bytes MPEG-TS serial output
• No coding mechanism
• Incoming MPEG_TS clock resynchronization
• x47 sync signal recovery
• Parallel/Serial Conversion
• Auto adaptation to 188/204/208 bytes packet Input
• 188 bytes MPEG-TS serial output
• No coding mechanism
特色
- Drop-in module for Xilinx Spartan-6, Virtex-6, Artix-7, Kintex-7, Virtex-7, Zynq FPGAs
- Full synthesizable RTL VHDL design (not delivered) for easy customization
可交付内容
- Datasheet
- Netlist for core generation
- VHDL top file
- VHDL source code : can be delivered as an option under NDA and other specific clauses
应用
- MVD MPEG TS Serializer may be used in applications related to DVB/MPEG-TS transport streams for Serial Data transmission between FPGA.
Block Diagram of the MPEG TS Serializer
查看 MPEG TS Serializer 详细介绍：
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MPEG TS
- Video over IP reference design (JPEG2000 or other compression scheme, MPEG-2 TS, support of SMPTE2022 standard)
- MPEG-2 Transport Stream Encapsulation for SMPTE2022
- MPEG Transport Stream with RTP / UDP / IP Hardware Stack
- Rx MPEG TS Interface
- MPEG-TS closed caption inserter
- MPEG-2 Transport Stream Demux