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MPEG-1/2 – Layer I/II Audio Decoder
The MPEG-1/2 – Layer I/II Audio Decoder (CWda75) is an audio IP core for decoding one audio stream in real-time.
This core contains the MPEG-1/2 – Layer I/II decoder software and the Coreworks processor based hardware audio engine platform (CWda1011).
The software is compiled into an image file (.bin) which can be automatically boot-loaded through one of the control interfaces (parallel AMBA APB or serial SPI) and run on the audio engine platform with simple parameters setting.
The program can be configured, controlled and monitored by means of a configuration, control, and status register file, accessed by the control interfaces.
The audio input and output interfaces uses a native parallel interface. Other standard audio interfaces, such as I2S/TDM and SPDIF are also available.
The interface to the external memory can be one of the following: AMBA AXI (for ASICs or Xilinx FPGAs), Avalon (for Altera FPGAs) or MIG (for Xilinx FPGAs).
The CWda1011 platform is an instance of the generic CWdaXYZ audio engine platform. Other platforms are available for a different number of audio channels (from 2 channels, up to 32 channels). Please contact us to select the best solution for your requirements.
This core contains the MPEG-1/2 – Layer I/II decoder software and the Coreworks processor based hardware audio engine platform (CWda1011).
The software is compiled into an image file (.bin) which can be automatically boot-loaded through one of the control interfaces (parallel AMBA APB or serial SPI) and run on the audio engine platform with simple parameters setting.
The program can be configured, controlled and monitored by means of a configuration, control, and status register file, accessed by the control interfaces.
The audio input and output interfaces uses a native parallel interface. Other standard audio interfaces, such as I2S/TDM and SPDIF are also available.
The interface to the external memory can be one of the following: AMBA AXI (for ASICs or Xilinx FPGAs), Avalon (for Altera FPGAs) or MIG (for Xilinx FPGAs).
The CWda1011 platform is an instance of the generic CWdaXYZ audio engine platform. Other platforms are available for a different number of audio channels (from 2 channels, up to 32 channels). Please contact us to select the best solution for your requirements.
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Block Diagram of the MPEG-1/2 – Layer I/II Audio Decoder
Audio IP
- H.264 Audio & Video Decoder IP
- Modern Audio DSP, designed for battery operated, high-performance, audio and voice applications
- Modern, high performance Audio DSP, optimized for far-field noise reduction and Artificial Intelligence speech recognition
- Spatial Audio & Head Tracking Solution
- SRC-Pro : 24-bit -130dB THD+N Multi-Channel Audio Asynchronous Sample Rate Converter
- LC3plus Audio Codec IP for Bluetooth LE Audio