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MIPS R2000 compatible core.
The Vr2000 is a synthesizable VHDL (soft) core design which is object code compatible with MIPS' popular R2000. The Vr2000 is intended to be used in system-on-a-chip applications constructed using gate-arrays or standard cells. It should be especially interesting to designers who currently use R2000s in embedded control applications and want to integrate its functionality with other designs/peripherals/etc. onto a single chip (ASIC).
The Vr2000 is a fully synchronous design and contains no microcode; all control is implemented via state machines. It is written in synthesizable VHDL using IEEE standard libraries. It uses a single clock.
The Vr2000 core interfaces to other on-chip periperals and memory using simple, synchronous interface.
The Vr2000 is implemented using a fully interlocked 5-stage pipeline.
The Vr2000 also contains debug assist hardware to provide "ICE"-like debugging access. This hardware is intended to be accessed through a JTAG port (a JTAG interface is also available).
The Vr2000 synthesizes to approximately 30 to 35 Kgates (this is very dependent upon the target libary) when using a typical standard cell libary.
The design kit includes the synthesizable VHDL model, a sample synthesis script, a sample constraint file, a VHDL test bench, and test stimulus files. Instructions and a build script are also included to create a software generation environment for embedded systems using the GNU gcc tools.
VLSI Concepts can provide customization of the design, if requested.
Design and integration assistance is also available from VLSI Concepts.
The Vr2000 is a fully synchronous design and contains no microcode; all control is implemented via state machines. It is written in synthesizable VHDL using IEEE standard libraries. It uses a single clock.
The Vr2000 core interfaces to other on-chip periperals and memory using simple, synchronous interface.
The Vr2000 is implemented using a fully interlocked 5-stage pipeline.
The Vr2000 also contains debug assist hardware to provide "ICE"-like debugging access. This hardware is intended to be accessed through a JTAG port (a JTAG interface is also available).
The Vr2000 synthesizes to approximately 30 to 35 Kgates (this is very dependent upon the target libary) when using a typical standard cell libary.
The design kit includes the synthesizable VHDL model, a sample synthesis script, a sample constraint file, a VHDL test bench, and test stimulus files. Instructions and a build script are also included to create a software generation environment for embedded systems using the GNU gcc tools.
VLSI Concepts can provide customization of the design, if requested.
Design and integration assistance is also available from VLSI Concepts.
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