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MIPI Universal D-PHY in TSMC 40nm ULP
The MXL-DPHY-UNIV is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Specification for D-PHY v1.1.
The IP can be configured as a MIPI Master or MIPI Slave optimized for CSI-2SM (Camera Serial Interface), and DSISM (Display Serial Interface) applications.
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.
The IP can be configured as a MIPI Master or MIPI Slave optimized for CSI-2SM (Camera Serial Interface), and DSISM (Display Serial Interface) applications.
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.
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Block Diagram of the MIPI Universal D-PHY in TSMC 40nm ULP
MIPI D-PHY Transmitter IP
- MIPI CSI-2 Transmitter v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI D-PHY DSI/CSI Transmitter IP (Silicon proven in TSMC 22ULP)
- MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- Globalfoundries 12nm MIPI D-PHY V1.2@2.5GHz