The MXL-DPHY-UNIV is a high-frequency low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v2.1, which is backward compatible with MIPI Specification for D-PHY v1.1. The PHY can be configured as a MIPI Master or MIPI Slave supporting camera interface CSI-2 and display interface DSI applications. The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.
- Consists of 1 Clock lane and up to 4 Data lanes.
- Supports MIPI® Alliance Specification for D-PHY Version 2.1.
- Supports both high speed and low-power modes.
- 80 Mbps to 1.5 Gbps data rate per lane without Deskew calibration.
- Up to 2.5 Gbps data rate per lane with Deskew calibration.
- 10 Mbps data rate in low-power mode.
- Low power dissipation.
- Loopback testability support.
- Optional resistance termination calibrator.
- Deskew calibration support.
- LVS netlist
- LEF & LIB files
- Verilog Model
- Timing Model
- Integration Guidlines
- Physical Verification Report
- One year support
- Consumer Electronics
Block Diagram of the MIPI Universal D-PHY in TSMC 22nm ULP