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MIPI SPMI Slave IP Core

MIPI SPMI Slave interface provides full support for the two-wire MIPI SPMI synchronous serial interface, compatible with SPMI specification. Through its SPMI companilitity, it provides a simple interface to a wide range of low-cost devices. The MIPI SPMI Slave IP Core is proven in FPGA enviroment.The host interface of the MIPI SPMI can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Wishbone or Custom protocol.

The MIPI SPMI Slave IP Core is supported natively in Verilog, VHDL and SystemC

特色

Supports 1.0 MIPI SPMI Specification
Full MIPI SPMI Slave functionality
Supports following frames

Command Frame
Data/Address Frame
No Response Frame

Support for slave requests through Alert bit.
Support for slave request hold.
Glitch suppression (optional).
Supports extended register read/writes
Supports wakeup command
Supports Authentication Command Sequence
Device Descriptor Block command Sequences
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple interface allows easy connection to microprocessor/microcontroller devices
Slave IP can be build to have additional slave interface blocks like SPI or I2C, in addition to SPMI slave functionality.

可交付内容

The MIPI Slave interface is available in Source and netlist products.
The Source product is delived in plain text verilog or VHDL or SystemC source code
Integration testbench and tests
Scripts for simulation and synthesis with support for common EDA tools
Documentation contains User's Guide and Release notes.