MIPI D-PHY Rx-Only 2 Lanes in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, N7, N6)
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MIPI RFFE Master Controller IP Core
Mobile radio communication is trending towards complex multi-radio systems comprising of several transceivers. The MIPI RFFE bus is is 2-wire serial interface which utilizes a bus frequency of up to 26 MHz and timing accurate trigger mechanisms to allow control of timing critical functions. It is used to connect a digital RFIC to RF front end components, like Power Amplifiers, Low-Noise Amplifiers and Antenna Sensors, which are considered RFFE Slaves.
The RFFE Master IP core typically resides in the RFIC in a mobile platform, and utilizes the RFFE bus to identify, program and monitor the registers in RF front end Slave devices through programmed IO. It is designed to support existing standards such as LTE, UMTS, HSPA and EGPRS, and is usable in configurations ranging from single Master/single Slave to multi-Master/multi-Slave.
At a minimum, Arasan delivers RFFE Master in RTL form. Optionally, physical designs of the complete RFFE Master, including the Pad Logic block for CLK and DATA as shown below, can be provided upon request.
The RFFE Master IP core typically resides in the RFIC in a mobile platform, and utilizes the RFFE bus to identify, program and monitor the registers in RF front end Slave devices through programmed IO. It is designed to support existing standards such as LTE, UMTS, HSPA and EGPRS, and is usable in configurations ranging from single Master/single Slave to multi-Master/multi-Slave.
At a minimum, Arasan delivers RFFE Master in RTL form. Optionally, physical designs of the complete RFFE Master, including the Pad Logic block for CLK and DATA as shown below, can be provided upon request.
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