Neural Network Processor for Intelligent Vision, Voice, Natural Language Processing
You are here:
MIPI Receiver,DPHY RX V1.2; UMC 28nm HPC Logic and Mixed-Mode Process
MIPI Receiver,DPHY RX V1.2; UMC 28nm HPC Logic and Mixed-Mode Process
查看 MIPI Receiver,DPHY RX V1.2; UMC 28nm HPC Logic and Mixed-Mode Process 详细介绍：
- 查看 MIPI Receiver,DPHY RX V1.2; UMC 28nm HPC Logic and Mixed-Mode Process 完整数据手册
- 联系 MIPI Receiver,DPHY RX V1.2; UMC 28nm HPC Logic and Mixed-Mode Process 供应商
Interface Solution IP
- Configurable PCI Express 4.0 Controller for ASIC/SoC with a configurable AMBA AXI3/AXI4 user interface
- Interlaken Protocol IP (High Speed Chip-To-Chip Interface)
- Configurable PCI Express 3.0, 2.0, 1.1 Controller IP for ASIC/SoC with AMBA AXI User Interface
- Very compact (500 LUTs) Camera Sensor Receiver Interface Converting from MIPI CSI-2 to AXI4-Stream Video Standard
- Common Public Radio Interface (CPRI) v.7.0 IPC
- Common Public Radio Interface (CPRI) v.6.1 IPC