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MIPI M-PHY v3.1 IP in TSMC(12/16nm, 28nm, 40nm, and 55nm)
M31 MIPI M-PHY is a serial interface technology with high bandwidth capabilities, which is particularly developed for mobile applications to obtain low pin counts along with excellent power efficiency. As a MIPI Alliance contributor and leading Interface IP provider, M31 provides silicon-proven and low-power M-PHY in different process nodes. The M-PHY IP follows MIPI M-PHY v3.1 spec and supports full range of high-speed (HS) and low-speed (LS) data transfer. It is compliant to the RMMI interface which allows seamless integration with upside controllers. The M-PHY IP is optimized for UFS (Universal Flash Storage) and DigRF applications. It supports not only a very short sync length for HS transmission but also a reference-less mode during LS operation. Meanwhile, M31 also provides various lane configurations for the M-PHY IP to meet different requirements of bandwidth.
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MIPI M-Phy IP
- MIPI M-PHY in TSMC (28nm, 16nm, 12nm, 10nm)
- UFS 2.1 Host Controller compatible with M-PHY 3.1 and UniPro 1.6
- MIPI M-PHY Gear4 IP (Silicon Proven in TSMC 12FFC)
- UFS 3.0 Host Controller compatible with M-PHY 4.0 and UniPro 1.8
- MIPI M-PHY G4 Designed For TSMC 28nm HPC+
- MIPI UFS v3.1 Host Controller IP, Compatible with M-PHY and Unipro