MIPI D-PHY Rx-Only 2 Lanes in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, N7, N6)
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MIPI M-PHY TX/RX + Controller
INNOSILICON M-PHY implements MIPI M-PHY protocol V4.1. The M-PHY protocol specification is a part of group of communication protocols defined by MIPI Alliance standards intended for mobile system chip to chip communications. The M-PHY specification is specifically targeted to be suitable for multiple protocols, and for a wide range of applications.
INNOSILICON M-PHY includes transmitters and receivers to implement full-duplex operations. The IP supports multiple BURST modes, including HS, LS for improved power efficiency, and multiple power saving modes where power consumption can be traded-off against recovery time. The INNOSILICON I/O and ESD are also built- in, providing a convenient, drop- in PHY. The design is optimized for high speed applications with robust timing and small silicon area.
The INNOSILICON M-PHY supports the electrical portion of MIPI M -PHY V4.1 standard and cost-effectively adds MIPI M-PHY V4.1 capability to any SOC.
INNOSILICON M-PHY includes transmitters and receivers to implement full-duplex operations. The IP supports multiple BURST modes, including HS, LS for improved power efficiency, and multiple power saving modes where power consumption can be traded-off against recovery time. The INNOSILICON I/O and ESD are also built- in, providing a convenient, drop- in PHY. The design is optimized for high speed applications with robust timing and small silicon area.
The INNOSILICON M-PHY supports the electrical portion of MIPI M -PHY V4.1 standard and cost-effectively adds MIPI M-PHY V4.1 capability to any SOC.
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