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MIPI M-PHY
The MXL-M-PHY-DIGRF is a high-frequency low-power, low-cost, Physical Layer IP that supports the MIPI® Alliance Standard for M-PHY and DigRF. The IP can be used as a physical layer for the Baseband to RFIC interface. It supports the DigRF v4 standard.
By using efficient BURST mode operation with scalable speeds, significant power savings can be obtained.
Selection of signal slew rate and amplitude allows reduction of EMI/RFI, while maintaining low bit error rates. The core employs Mixel’s Logarithmic approach, enabling efficient implementation of multiple configurations.
By using efficient BURST mode operation with scalable speeds, significant power savings can be obtained.
Selection of signal slew rate and amplitude allows reduction of EMI/RFI, while maintaining low bit error rates. The core employs Mixel’s Logarithmic approach, enabling efficient implementation of multiple configurations.
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MIPI M-PHY IP
- MIPI M-PHY in TSMC (28nm, 16nm, 12nm, 10nm)
- UFS 2.1 Host Controller compatible with M-PHY 3.1 and UniPro 1.6
- MIPI M-PHY v3.1 IP in TSMC(12/16nm, 28nm, 40nm, and 55nm)
- UFS 3.0 Host Controller compatible with M-PHY 4.0 and UniPro 1.8
- MIPI M-PHY G4 Designed For TSMC 28nm HPC+
- MIPI D-PHY Receiver in TSMC 28nm HPM