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MIPI M-PHY
The MXL-M-PHY-DIGRF is a high-frequency low-power, low-cost, Physical Layer IP that supports the MIPI® Alliance Standard for M-PHY and DigRF. The IP can be used as a physical layer for the Baseband to RFIC interface. It supports the DigRF v4 standard.
By using efficient BURST mode operation with scalable speeds, significant power savings can be obtained.
Selection of signal slew rate and amplitude allows reduction of EMI/RFI, while maintaining low bit error rates. The core employs Mixel’s Logarithmic approach, enabling efficient implementation of multiple configurations.
By using efficient BURST mode operation with scalable speeds, significant power savings can be obtained.
Selection of signal slew rate and amplitude allows reduction of EMI/RFI, while maintaining low bit error rates. The core employs Mixel’s Logarithmic approach, enabling efficient implementation of multiple configurations.
特色
- Supports the MIPI Standard for M-PHY, Draft Specification v0.90.00-r02 and DigRF v4 V1.10.00.0.04
- Dual-simplex point-to-point interface with ultra low voltage differential signaling
- Slew-rate control for EMI reduction
- Supports HS mode (GEAR 1-2, A & B)
- Supports LS mode (Sys-Burst)
- 1.25-3Gbps data rate in HS mode
- 19.2-52Mbps data rate in LS mode
- Suitable for copper and optical media
- Mixel’s Logarithmic approach efficiently supports large number of different configurations
- Low power dissipation
可交付内容
- Data Sheet/Specifications
- GDSII data base
- LVS Netlist
- Integration Guidelines
- Timing Model
- Behavioral Model
- LEF File & RTL
查看 MIPI M-PHY 详细介绍：
- 查看 MIPI M-PHY 完整数据手册
- 联系 MIPI M-PHY 供应商
MIPI M-PHY
- MIPI M-PHY G4 Designed For TSMC 28nm HPC+
- MIPI M-PHY in TSMC (28nm, 16nm, 12nm, 10nm)
- UFS 2.1 Host Controller compatible with M-PHY 3.1 and UniPro 1.6
- UFS 2.1 Device Controller compatible with MIPI M-PHY 3.1 and UniPro 1.6
- MIPI M-PHY - TSMC 40nm
- UFS 3.0 Host Controller with AES Encryption compatible with M-PHY 4.0 and UniPro 1.8