MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
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MIPI M-PHY in SMIC 130nm
The MXL-MPHY-S-130 is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI Alliance Standard for M-PHY. The IP can be used as a physical layer for many applications, including interfaces for display, camera, audio, video, memory, power management and Baseband to RFIC.
It supports the following standards: DigRF v4, CSI-3, DSI-2, Uniport-M (UniPro1.41) LLI and JC-64.1 UFS.
By using efficient BURST mode operation with scalable speeds, significant power savings can be obtained.
Selection of signal slew rate and amplitude allows reduction of EMI/RFI, while maintaining low bit error rates.
It supports the following standards: DigRF v4, CSI-3, DSI-2, Uniport-M (UniPro1.41) LLI and JC-64.1 UFS.
By using efficient BURST mode operation with scalable speeds, significant power savings can be obtained.
Selection of signal slew rate and amplitude allows reduction of EMI/RFI, while maintaining low bit error rates.
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Block Diagram of the MIPI M-PHY in SMIC 130nm
