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MIPI LLI Controller IP Core
The MIPI LLI Controller IP Core resides on each instance of a chip pair, and the two controllers communicate at a physical level through the M-PHY and their associated differential signals. The MIPI LLI Controller IP requires the LLI specific MIPI M-PHY Type I IP as the Physical Layer and supports 1, 2, 3, 4 or 6 Lanes. The LLI Controller/M-PHY pairs on each chip together form a Low Latency Interface (LLI) bridge between the system buses/interconnects of two companion chips. This core is designed to be configurable as either a system bus master or slave, or both, for the Low Latency (LL) and Best Effort (BE) traffic classes defined in the MIPI LLI specification.
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Block Diagram of the MIPI LLI Controller - (Low Latency Interface)
