Original Lossless codec IP core - Full HD 30fps@126MHz (1Sample/clk)
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MIPI I3C Basic v1.1.1 specifications with Host Controller Interface v1.1 specification
The I3C (Improved Inter-Integrated Circuit) is the successor of the I2C bus. Keeping the best assets from its elder brother, the I3C has major improvements in use and power, and performance. The Core uses just two pins and consumes a fraction of the energy, reducing cost and complexity while allowing multiple sensors from different vendors to be easily interfaced with a controller or application processor.
DCD maintains backward compatibility, enabling a smooth transition from I2C to I3C and simple implementation. The newest Core offers a flexible multi-drop interface between a host processor and peripheral sensors, to support the growing usage of sensors in embedded systems. The same I3C standardizes sensor communication, reduces the number of physical pins used in sensor system integration, and supports low-power, high-speed, and other critical features that are currently covered by I2C and SPI.
DCD maintains backward compatibility, enabling a smooth transition from I2C to I3C and simple implementation. The newest Core offers a flexible multi-drop interface between a host processor and peripheral sensors, to support the growing usage of sensors in embedded systems. The same I3C standardizes sensor communication, reduces the number of physical pins used in sensor system integration, and supports low-power, high-speed, and other critical features that are currently covered by I2C and SPI.
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