You are here:
MIPI DPHY RX
This MIPI D-PHY IP is designed to compliant with the MIPI D-PHY v1.2 specifications. It is designed for low power and high-performance application. The primary application is for the physical layer CSI-2 (Camera Serial Interface). Other applications that require a high data rate serial link may also benefit from the implementation of the D-PHY. The D-PHY implementation for CSI will provide 1 clock and 4 data lanes operating at a maximum high speed bit rate of 1600Mbps per data channel. The 4 data lanes also support low power data communication operating at a maximum bit rate of 10Mbps.
查看 MIPI DPHY RX 详细介绍:
- 查看 MIPI DPHY RX 完整数据手册
- 联系 MIPI DPHY RX 供应商
MIPI D-PHY IP
- MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI DSI Receiver Controller v1.3
- MIPI DSI Transmit Controller v1.3
- MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)