MIPI DPHY RX

This MIPI D-PHY IP is designed to compliant with the MIPI D-PHY v1.2 specifications. It is designed for low power and high-performance application. The primary application is for the physical layer CSI-2 (Camera Serial Interface). Other applications that require a high data rate serial link may also benefit from the implementation of the D-PHY. The D-PHY implementation for CSI will provide 1 clock and 4 data lanes operating at a maximum high speed bit rate of 1600Mbps per data channel. The 4 data lanes also support low power data communication operating at a maximum bit rate of 10Mbps.

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