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MIPI D-PHY v1.2/LVDS/TTL combo PHY(supporting CSI/DSI)
The INNO_MIPI D-PHY is a MIPI® V1.0 compliant solution available in both Tx or Rx configuration. Each PHY supports high-speed 1.5 GHbps data transfer combined with a MIPI® low-power bi-directional transceiver. Controller communication is via the integrated PPI and supports CSI, DSI and UniPro™. The PHY can be configured to support all modes listed in the MIPI® V1.0 specification.
A CSI controller is also available.
A CSI controller is also available.
特色
- Available with HS Tx or Rx
- Compliant with MIPI® v1.0
- PHY Protocol Interface (PPI) interfaces to CSI, DSI and UniPro™
- 1.5 GHbps maximum data transfer rate per lane
- Configurable from 1-4 data lanes
- HS, LP and ULPS modes
- Unidirectional and bi-directional modes supported
- Automatic termination control
- Sequence error detection on Rx
- Low-Power dissipation: HS less than 40mA/Lane
- Built in LDO and low jitter PLL
- Compact die size: 0.5mm2 per lane
- Optionally supports LVDS and HiSPI
可交付内容
- We can provide the following deliverables to aid quick and reliable integration into the design flow. Please contact us for any additional views:
- GDSII
- Netlist (Spice format for LVS)
- Footprint (LEF format)
- User documentation
- Module integration guidelines
- Datasheet
- Silicon validation report
- Evaluation board
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