USB 3.1 PHY (10G/5G) in Samsung (14nm, 10nm, 11nm, 8nm, 5nm)
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MIPI D-PHY Universal Lane 16FFC IP for Automotive
The MXL-DPHY-UNIV is a high-frequency low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v1.2.
The IP can be configured as a MIPI Master or MIPI Slave optimized for CSI-2SM (Camera Serial Interface), and DSISM (Display Serial Interface) applications.
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.
The D-PHY supports a bit rate range of 80 to 1500 Mbps per Lane without deskew calibration and up to 2500 Mbps with deskew calibration.
The maximum data rate in low-power mode is 10 Mbps. For a fixed clock frequency, the available data capacity of a PHY configuration can be increased by using more lanes. Effective data throughput can be reduced by employing burst mode communication.
The IP can be configured as a MIPI Master or MIPI Slave optimized for CSI-2SM (Camera Serial Interface), and DSISM (Display Serial Interface) applications.
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.
The D-PHY supports a bit rate range of 80 to 1500 Mbps per Lane without deskew calibration and up to 2500 Mbps with deskew calibration.
The maximum data rate in low-power mode is 10 Mbps. For a fixed clock frequency, the available data capacity of a PHY configuration can be increased by using more lanes. Effective data throughput can be reduced by employing burst mode communication.
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Block Diagram of the MIPI D-PHY Universal Lane 16FFC IP for Automotive
