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MIPI D-PHY Universal IP in TSMC 40LP-eF
The MXL-DPHY-UNIV is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Specification for D-PHY v1.1. The IP can be configured as a MIPI Master or MIPI Slave optimized for CSI-2 (Camera Serial Interface), and DSI (Display Serial Interface) applications. The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control
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Block Diagram of the MIPI D-PHY Universal IP in TSMC 40LP-eF
Video Demo of the MIPI D-PHY Universal IP in TSMC 40LP-eF
In this Mixel customer demo video, we see Mixel’s MIPI D-PHY IP integrated into the Hercules Microelectronics HME-H1D03 FPGA, configured as a Human Machine Interface (HMI) solution based, which can be used for smart home appliances such as refrigerator, ventilator, air conditioning control panel. In this demo, we see the GUI for refrigerator control. Mixel provided our MIPI D-PHY Universal IP.
For more information, visit: https://mixel.com/mixel-d-phy-ip-hme-fpga-processor/
For more information about the HME-H1D03 FPGA, visit:
http://en.hercules-micro.com/content/details86_596.html
MIPI D-PHY IP
- MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI DSI Receiver Controller v1.3
- MIPI DSI Transmit Controller v1.3
- MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)