You are here:
MIPI D-PHY Universal IP in SMIC 130nm
The MIPI D-PHY Transmitter is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY Designed for SMIC 130nm.
The IP can be configured as a MIPI master or slave and consists of 5 lanes: 1 Clock lane and 4 data lanes.
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
The IP can be configured as a MIPI master or slave and consists of 5 lanes: 1 Clock lane and 4 data lanes.
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
查看 MIPI D-PHY Universal IP in SMIC 130nm 详细介绍：
- 查看 MIPI D-PHY Universal IP in SMIC 130nm 完整数据手册
- 联系 MIPI D-PHY Universal IP in SMIC 130nm 供应商
Block Diagram of the MIPI D-PHY Universal IP in SMIC 130nm
MIPI D-PHY Transmitter IP
- MIPI CSI DSI Controller - CPHY CSI-2 Transmitter v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 28HPC+
- MIPI D-PHY CSI-2 TX+ (Transmitter) IP in TSMC 22ULL
- MIPI C-PHY/D-PHY Combo CSI-2 TX (Transmitter) in TSMC 40ULP
- MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)