Original Lossless codec IP core - Full HD 30fps@126MHz (1Sample/clk)
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MIPI D-PHY Universal IP in Samsung 28FDSOI
The MXL-DPHY-UNIV is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY can be configured as a MIPI Master or MIPI Slave supporting camera interface CSI-2 v1.2 and display interface DSI v1.3 applications. The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.
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Block Diagram of the MIPI D-PHY Universal IP in Samsung 28FDSOI
Video Demo of the MIPI D-PHY Universal IP in Samsung 28FDSOI
In this Mixel customer demo video, we see Mixel’s MIPI D-PHY IP integrated into the Lattice CrossLink-NX FPGA, the world’s first low-power FPGA to support D-PHY v1.2 with 2.5Gbps per lane and the previous generation FPGA, Lattice Crosslink which was the first bridge supporting 12 Gbps of Aggregate Bandwidth.
Built using the new 28 nm FD-SOI Lattice Nexus™ FPGA platform, the CrossLink-NX FPGAs outperform FPGAs of similar class in terms of power, form factor, reliability, and performance. The CrossLink-NX FPGAs were developed for use in applications including sensor and display bridging, sensor aggregation, sensor duplication, and AI inferencing at the Edge.
The previous generation Lattice CrossLink bridge combines the flexibility and fast time to market of an FPGA with the power and functional optimization of an ASSP to create a new product class called programmable ASSP (pASSP™). This solution, which is now going into production, integrates Mixel’s high performance, low power Universal MIPI D-PHY, implemented in UMC’s 40nm process to achieve first silicon success.