MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
You are here:
MIPI D-PHY Tx v1.1 ONLY @1.5ghz Ultra Low Power & Low Area for IoT & Wearables
Arasan 2nd Generation MIPI D-PHY v1.1 IP supporting speeds of up to 1.5 Gbps on TSMC 22nm process technology for
SoC designs. Arasan’s D-PHY IP is available on both TSMC’s industry-leading 22nm ultra-low power (22ULP) and 22nm ultra-low leakage (22ULL) process
technologies. TSMC 22nm ultra-low power (22ULP) is an ideal foundry technology for applications including image processing,
digital TVs, set-top boxes, smartphones and consumer products in terms of its power, performance and area (PPA) optimization,
while its 22nm ultra-low leakage (22ULL) technology provides significant power reduction to support IoT and wearable
device applications, where power is of paramount importance. MIPI D’Phy as a physical serial communicating layer is gaining traction in the today’s power hungry mobile
and mobile related applications due to its low power consumption operation.
The D-PHY IP is also available as a Rx only IP for companies looking to save silicon area and further improve power consumption.
The MIPI D-PHY IP is seamlessly integrated with Arasan’s own DSI Tx and DSI Rx IP Cores as part of its
Total MIPI Display IP Solution for wearables and IoT.
Arasan’s Tx⁺ configuration has smaller area and standby current, as only two transmitters are need instead of the five transmitters that would be needed for a conventional 4 data-lanes Universal lane configuration.
The reduction in area is about 40% while standby power reduction is about 60%.
Arasan has been a contributing member to the MIPI Association 2005 with over a billion chips shipped with its MIPI IP.
Arasan MIPI D-PHY IP is proven on its own test chip on TSMC 28nm process, which has been licensed by multiple customers since 2016
and validated along with its CSI IP and DSI IP with 3rd Party VIP as a Total IP Solution. The company’s MIPI CSI, DSI, DPHY and
CPHY IP are also used in compliance and production testers further attesting the quality and compliance of Arasan IP.
The MIPI D-PHY IP is also available off the shelf on the TSMC 40nm, 28nm, 16nm and 12nm process technologies.
A D-PHY / C-PHY Combo HDK based on Arasan’s ASIC applications on TSMC 28nm process is also available to licensees of
Arasan’s DPHY IP or CPHY IP to prototype their Display or Imaging products before going to production.
Customers can license with confidence in Arasan’s MIPI D-PHY IP knowing they can prototype
with the real silicon on TSMC 28nm process, which is used in a MIPI Compliance Tester to test for MIPI CSI, DSI, D-PHY
and C-PHY Standards Compliance. We are Compliance!
SoC designs. Arasan’s D-PHY IP is available on both TSMC’s industry-leading 22nm ultra-low power (22ULP) and 22nm ultra-low leakage (22ULL) process
technologies. TSMC 22nm ultra-low power (22ULP) is an ideal foundry technology for applications including image processing,
digital TVs, set-top boxes, smartphones and consumer products in terms of its power, performance and area (PPA) optimization,
while its 22nm ultra-low leakage (22ULL) technology provides significant power reduction to support IoT and wearable
device applications, where power is of paramount importance. MIPI D’Phy as a physical serial communicating layer is gaining traction in the today’s power hungry mobile
and mobile related applications due to its low power consumption operation.
The D-PHY IP is also available as a Rx only IP for companies looking to save silicon area and further improve power consumption.
The MIPI D-PHY IP is seamlessly integrated with Arasan’s own DSI Tx and DSI Rx IP Cores as part of its
Total MIPI Display IP Solution for wearables and IoT.
Arasan’s Tx⁺ configuration has smaller area and standby current, as only two transmitters are need instead of the five transmitters that would be needed for a conventional 4 data-lanes Universal lane configuration.
The reduction in area is about 40% while standby power reduction is about 60%.
Arasan has been a contributing member to the MIPI Association 2005 with over a billion chips shipped with its MIPI IP.
Arasan MIPI D-PHY IP is proven on its own test chip on TSMC 28nm process, which has been licensed by multiple customers since 2016
and validated along with its CSI IP and DSI IP with 3rd Party VIP as a Total IP Solution. The company’s MIPI CSI, DSI, DPHY and
CPHY IP are also used in compliance and production testers further attesting the quality and compliance of Arasan IP.
The MIPI D-PHY IP is also available off the shelf on the TSMC 40nm, 28nm, 16nm and 12nm process technologies.
A D-PHY / C-PHY Combo HDK based on Arasan’s ASIC applications on TSMC 28nm process is also available to licensees of
Arasan’s DPHY IP or CPHY IP to prototype their Display or Imaging products before going to production.
Customers can license with confidence in Arasan’s MIPI D-PHY IP knowing they can prototype
with the real silicon on TSMC 28nm process, which is used in a MIPI Compliance Tester to test for MIPI CSI, DSI, D-PHY
and C-PHY Standards Compliance. We are Compliance!
查看 MIPI D-PHY Tx v1.1 ONLY @1.5ghz Ultra Low Power & Low Area for IoT & Wearables 详细介绍：
- 查看 MIPI D-PHY Tx v1.1 ONLY @1.5ghz Ultra Low Power & Low Area for IoT & Wearables 完整数据手册
- 联系 MIPI D-PHY Tx v1.1 ONLY @1.5ghz Ultra Low Power & Low Area for IoT & Wearables 供应商