You are here:
MIPI D-PHY Transmitter in TSMC 28nm LP
The MIPI D-PHY Transmitter is a high-frequency low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI Alliance Standard for D-PHY.
The IP can be configured as a MIPI master or slave and consists of 5 lanes: 1 Clock lane and 4 data lanes.
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
The IP can be configured as a MIPI master or slave and consists of 5 lanes: 1 Clock lane and 4 data lanes.
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
查看 MIPI D-PHY Transmitter in TSMC 28nm LP 详细介绍：
- 查看 MIPI D-PHY Transmitter in TSMC 28nm LP 完整数据手册
- 联系 MIPI D-PHY Transmitter in TSMC 28nm LP 供应商
MIPI D-PHY IP
- MIPI D-PHY in TSMC (40nm, 28nm, 16nm, 12nm, 7nm)
- MIPI CSI-2 Transmitter v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI C-PHY-D-PHY Combo PHY IP on TSMC 28nm HPC+
- MIPI C-PHY and D-PHY Combo
- MIPI D-PHY Universal Lane 16FFC IP for Automotive
- MIPI Universal D-PHY IP - 4.5Gbps/lane, MIPI D-PHY v2.5 Compliant